Computer Organization
Q171.
In X=(M+NxO)/(PxQ), how many one-address instructions are required to evaluate it?Q172.
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)_{16} and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)_{16}. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows: Store the current value of PC in the stack Store the value of PSW register in the stack Load the starting address of the subroutine in PC The content of PC just before the fetch of a CALL instruction is (5FA0)_{16}. After execution of the CALL instruction, the value of the stack pointer isQ173.
A non-pipelined CPU has 12 general purpose registers?(R0,R1,R2,...,R12). Following operations are supportedADD Ra, Rb, Rr Add Ra to Rb and store the result in RrMUL Ra, Rb, Rr Multiply Ra to Rb and store the result in RrMUL operation takes two clock cycles, ADD takes one clock cycle.Calculate minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variable X,Y,Z are initially available in registers R0,R1 and R2 and contents of these registers must not be modified.Q174.
Consider the following data path diagram. Consider an instruction: R0\leftarrow R1+R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively. 1. \; R2_r,TEMP1_r,ALU_{add},TEMP2_w 2. \; R1_r,TEMP1_w 3. \; PC_r,MAR_w,MEM_r 4. \; TEMP2_r,R0_w 5. \; MDR_r,IR_w Which one of the following is the correct order of execution of the above steps?Q175.
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will beQ176.
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________.Q179.
How many number of times the instruction sequence below will loop before coming out of the loop? MOV AL, 00H A1: INC AL JNZ A1Q180.
Assume that 16-bit CPU is trying to access a double word stating at an odd address. How many memory operations are required to access the data?